1. Field of the Invention
The invention relates to the fabrication of interconnecting means in MOS integrated circuits.
2. Prior Art
Interconnecting means are frequently employed in MOS integrated circuits to interconnect devices on a substrate and to provide lines for external connections. These interconnects are typically fabricated from polycrystalline silicon or metal such as aluminum, or are highly doped regions in the substrate, referred to as crossunders.
With current n-channel, silicon gate, MOS processing the crossunder interconnects are doped simultaneously with the doping of the source and drain regions. Typically, a polycrystalline silicon layer is masked to define the silicon gates and silicon interconnecting lines, and also to define the location of sites of crossunders. After this layer and an underlying gate oxide layer are etched the substrate is then subjected to a phosphorus dopant. In this manner, the source and drain regions and crossunders are formed in the substrate, and the polycrystalline silicon gates and lines are simultaneously doped. Where the phosphorus predeposition occurs at approximately 950.degree. C, the resistance of the diffused crossunders in the silicon substrate is approximately 10 ohms/sq. By way of comparison the polycrystalline silicon formed in this process has a resistance of approximately 30 ohms/sq. (The lower resistance of the crossunders when compared to the polycrystalline silicon, stems from the high carrier mobility of electrons in the monocrystalline silicon). This process provides relatively low resistance in all layers, however, because of the deep diffusion in the substrate the resultant devices have relatively high Miller and junction capacitance.
Recently there has been a trend in MOS processing to improve device performance by employing shallower source and drain regions. These shallower regions provide higher performance since the Miller and junction capacitance is reduced. By way of example, where phosphorus doping occurs at approximately 850.degree. C the resistance of crossunders formed along with the formation of the source and drain regions is approximately 25 ohms/sq. and the resistance of the doped polycrystalline silicon is approximately 80 ohms/sq. Thus, while a device fabricated in this manner provides improved performance the resistance of the diffused silicon and doped polycrystalline silicon is substantially increased.
In some cases arsenic is employed as a dopant for the source and drain regions to provide even shallower regions. The crossunders and polycrystalline silicon which are ion implanted simultaneously with the formation of the source and drain regions have relatively high resistance. For example, where the arsenic concentration from this ion implantation is approximately 3 .times. 10.sup.15 /cm.sup.2, the resistance of the diffused crossunders is approximately 30 ohms/sq. and the resistance of the polycrystalline silicon is approximately 100 ohms/sq.
The invented process provides relatively low resistance crossunders (e.g. 10 ohms/sq.) without substantial alteration to the standard, n-channel, silicon gate process referred to above. The disclosed process is particularly useful where the shallower arsenic or phosphorus source and drain regions are employed, although it may be used with the deeper phosphorus source and drain regions.